The GAL20V8, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (< 100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20V8 are the PAL architectures listed in the table of the macrocell description section. GAL20V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 10% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Datasheet – GAL20V8
- High Performance E2CMOS Technology
- 50% to 75% Reduction in Power from bipolar
- Active Pull-ups on all pins
- E2 Cell Technology
- Eight Output logic Macrocells
- Preload and power-on reset of all registers
- Electronic Signature for Identification